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The Cursor for Chip Design - Delivering Silicon-Ready Chip Designs…
SigmanticAI is building an AI-native hardware development assistant that automates the entire RTL design flow, from natural language to synthesizable HDL and testbenches, inside a seamless VSCode fork. Powered by fine-tuned Verilog LLMs, reinforcement learning, and real compiler feedback, SigmanticAI iteratively refines code until it compiles and passes synthesis, no matter how complex the design. It’s like the Cursor for HDL design. In addition to code generation, SigmanticAI can generate token-level annotations and onboarding documents to accelerate ramp-up for new engineers. With support for both cloud and on-prem deployment, it integrates with existing EDA tools to dramatically reduce debug time, improve collaboration, and accelerate hardware design across teams
SigmanticAI offers an interactive AI agent designed for hardware verification and RTL work, enabling users to generate complete VIP and IP from natural language and run within their existing EDA toolchains. It positions itself as a specialized alternative to Claude Code and Cursor, focused on chip design with verification-first workflows and persistent design context.
An interactive AI agent that reads user files, edits code, runs simulations, and orchestrates 14+ specialist agents to generate complete VIP and IP. It integrates with multiple simulators (Questa, VCS, Xcelium, Verilator, etc.) and auto-generates project Makefiles, configs, and compile scripts tailored to the user’s EDA stack. The system includes a persistent Brain Cache knowledge graph (.sigmanticaicache/) to maintain context across sessions and supports a convergence loop (compile → simulate → fix → 90%+ coverage) with data- and verification-first outputs (UVM testbenches, SVA, RAL, coverage, RTL). It runs via a Python pip install (sigmanticai) and works with any simulator, toolchain, or open-source option, with zero vendor lock-in.
Who it’s for: Chip design teams, hardware verification engineers, and RTL developers working with custom chip projects and defense/semiconductor workloads.
Backed by Y Combinator; active product with pip install, free starter, and enterprise/on-prem mention; multiple references to production-ready VIP/IP generation and convergence workflows.
AmazonI’m Rohil Khare, Co-Founder of SigmanticAI. I studied EECS at UC Berkeley and previously worked at Amazon. In high school, I filed provisional patents in IoT as an early innovator, and since then I’ve worked at multiple startups at the intersection of hardware and machine learning. At Berkeley, I conducted research at BAIR and the Architecture Group, and published at ICRA. Now, at SigmanticAI, I’m building AI-native tooling that accelerates the creation of custom chip designs and silicon.
I'm Tamzid Razzaque, Co-Founder of SigmanticAI. I studied EECS at UC Berkeley, with a focus on integrating AI applications with custom hardware design. I am continuing this passion at YC. I previously worked at Apple on custom circuits and researched at BWRC and BETR on custom FPGA accelerators.
Suite of AI Agents and Tools to Accelerate HDL (Hardware Description Language) Design
SigmanticAI releases a suite of AI-native HDL tools that convert natural language to synthesizable Verilog and testbenches, provide RL-driven debugging, onboard/documentation generation, and enable cloud or on-prem deployments with VS Code integration and compatibility with Cadence/Synopsys tools. Targets FPGA, custom chips, ML accelerators, and RISC-V/EDA workflows; claims 90%+ VerilogEval accuracy and a completed RISCV CPU project with their tooling.
Formerly “BitForge” · why startups rename →
The copilot for chip designers
An AI-powered test and debug platform for chip developers
