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Design a chip in minutes
Partcl modernizes chip design automation with physics-informed models powered by GPU acceleration. Our tools run up to 700× faster than legacy solutions, cutting weeks off development and unlocking AI-driven optimization.
CEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.
CTO at Partcl. Previously built embedded ML models at Apple, laser weeding robots at Carbon Robotics, and warehouse automation robots at Fulfil Solutions. Built and launched multiple rockets while running the avionics team at Space Enterprise at Berkeley, Stanford EECS PhD (dropout), UC Berkeley Physics.
Accelerate time to market for a new chip with Partcl.
Partcl speeds up ASIC physical design by rearchitecting algorithms for GPUs, reducing design-cycle time from weeks to minutes. It provides faster timing analysis, gate resizing, and placement, targeting AI accelerators, embedded/IoT, and mobile SoCs to shorten tapeouts and decrease non-recurring engineering costs.
Formerly “AionCAD” · why startups rename →
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